Agile and Cost-Efficient Chip Design with Chiplet Technology


Chip Technology


Agile and Cost-Efficient Chip Design with Chiplet Technology 


The revolution of big data and machine learning is posing unprecedented demand for computation resource, which requires more and more transistors to be integrated on chip. However, with the end of Dennard scaling and the slowdown of Moore’s law, it becomes very challenging and cost-inefficient to design such a sophisticated SoC with ever growing die size requirement. For example, the die area footprint of Hanguang is as large as 709mm²with 12nm process. Large designs are sometimes reticle limited and usually, which can lead to a lower yield of fabrication. Therefore, Chiplet technique becomes a promising method to tackle this problem.

Smaller chips have a higher yield, as a fixed number of defects per wafer breaks fewer total chips as the number of chips on a wafer grows. Smaller chips are simpler and easier to design. A system can mix silicon dice from different process nodes to improve design reuse and reduce cost. In the field of AI accelerator, the acceleration of a large network can be achieved by quickly and easily repackaging existing chips into an optimally sized system without waiting for the long development and fabrication process of new chips.

Couple of important considerations should be carefully taken into account before enabling chiplet technology in agile chip design in the post-Moore’s law area. For example, with chiplet technology, chip-to-chip communication is more expensive than traditional on-chip communication, which means we need to smartly allocate data into different chips of the Chiplet system. In addition, the communication protocols and scaling out solutions are more important considering the nature idea of the chiplet technology. 


  • Chiplet-based system architecture of high-performance scalable-AI accelerator.
  • Automated tool chain for data allocation under the Chiplet scenario in order to minimize off-chip memory access, on-chip memory footprint, and chip-to-chip communication.
  • Upper-level protocol standards and corresponding hardware architecture for intra/inter chiplet interconnection 
  • Advanced packaging technology for chiplet, such as active interposer, high-density Fan-Out technologies, etc.

Related Research Topics

  • Chiplet system
  • AI accelerator
  • DNN dataflow architectures
  • Software-hardware co-design
  • Electronic Design Automation (EDA)


Suggested Collaboration Method

AIR (Alibaba Innovative Research), one-year collaboration project. 

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