Agile chip development – design and verification

Research Themes



The high cost and long cycle of chip development have severely hindered innovations. The main reason for this is the design productive gap: the design complexity of the chip (# of gates/chip area) continues to grow at a compound annual growth rate (CAGR) of 58%, while the improvement in design capability (# of gates/Staff-month) via the current methodology is only at a compound annual growth rate of 23%. In order to make up for the gap between chip complexity and design capabilities, common practices can only solve the problem by extending the development cycle or increasing the manpower allocation, which raises the overall development cost of a chip design.

With the emergence of advanced hardware description languages (such as Chisel, high-level synthesis), scalable hardware generators, open instruction sets (such as RISC-V), AI-assisted EDA tools, the combination of such technologies has triggered a series of "chemical reactions". At this turning point, we are likely to call for collaborations and enable the innovations of chip design methodology to a new level.


  • A novel Design Space Exploration (DSE) engine to automatically approach the optimal design choice or pareto-frontier in a vast design space, and to simultaneously pursue many complex objectives, formulated in the performance space of chip design (PPA);
  • An Intelligent Test Selection (ITS) method to achieve the same coverage with fewer test vectors during the verification process;
  • A set of comprehensive experiments to demonstrate the effectiveness of DSE and ITS on Chisel or HLS-based hardware generators, in terms of quality-of-results (QoR) and time-to-results (TTR).

Related Research Topics

  • RISC-V/ISP/Codec microarchitecture design space exploration framework
  • Learning-based automatic design flow parameter tuning methods
  • Fast and accurate estimation of quality of results
  • Leveraging prior knowledge for effective DSE with transfer learning
  • Flexible multiple-objective reinforcement learning for chip design optimizations
  • Machine learning for test set redundancy and diagnosis complexity reductions

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