Research on Frontier Technologies in Data Center and Server
In recent years, video technology has developed rapidly. At the same time, video application scenarios are becoming more abundant. Typical application scenarios include live video streaming / short video clips / video conferences / telecommuting / virtual reality and so on. In order to achieve high-quality video compression and transmission, related organizations have developed a series of video coding standards, such as H.264/AVC and H.265/HEVC. Based on these popular video coding standards, a lot of software and hardware solutions for video codec has been derived to solve the problems of video compression in practical applications. However, traditional video encoder in the software side relies on CPU to implement the motion estimation and other procedures, which is difficult to meet the exponentially increasing for computing power with the development of coding standards. Considering the huge occupancy of CPU resources by software encoders, it is difficult to cater to the trends for real-time and miniaturization of video encoders in actual application scenarios. Compared with software encoders, hardware encoders make full use of the high parallelism of related algorithms. The hardware encoders can increase the calculation density by more than ten times and save the energy consumption of the servers by more than ten times than the software encoders in the general computing platform. At present, Internet companies at home and aboard (for example, Google / Amazon / Huawei / Bytedance / Tencent / Kuaishou) have invested heavily in the development of video hardware encoders. Hardware encoders are expected to save hundreds of millions of dollars each year for these companies. It can be seen that video hardware encoders are an important development direction in the future. At the same time, it is also a key chip technology that the country or enterprise needs to master.
In order to achieve a breakthrough in the hardware encoder, our team has set the goal of achieving the lowest cost and best virtual quality in the industry, and carried out a lot of research and development work. The hardware encoder that we propose integrates multiple functions of video encoding and processing, save the cost of customers and upgrade the video viewing experience. At the same time, the reduction of power consumption has also contributed to environmental protection.
We are currently advancing the research of next-generation video hardware encoders. Our goal is to further improve the video quality and be compatible with more video coding standards. By controlling the cost of the chip, our company can provide better video services with lower machine and bandwidth cost.
- Complete the algorithm development of H.266/VVC hardware coding. Compared with the common chip solutions of the H.265/HEVC encoder in the market, the compression rate is expected to increase by more than 25%. Compared with the existing H.265 hardware coding algorithm, the encoding algorithm complexity of VVC is expected to increase by no more than 50%.
- Complete C MODEL of H.266/VVC encoding algorithm. The architecture is compatible with the existing H.265 encoding architecture, and completes the cross-validation with the encoding algorithm.
- It is expected that the partner can complete 2 technical patent applications.
- Expect the partners to deliver code, algorithm design documents and quarterly progress reports.
Related Research Topics
- Video Compression and Processing
- Versatile Video Coding (VVC) standard
- Video Coding Mode Decision
- Hardware implementation and optimization for Video Coding
- To improve the coding algorithm performance of H.266/VVC for hardware design
- To reduce the cost and power consumption of the hardware implementation
- A Low Power Versatile Video Coding (VVC) Loop Filter Hardware
- Adaptive CU Split Decision for VVC encoding