- System Architecture
Focuses on system software and hardware design including instruction set architecture, programming languages, and compiler technologies for new computing platform.
- New Computing Technologies
Circuit, architecture, and applications with new computing technologies, such as 3D IC design, approximate computing, ultra-low power chip design, and edge computing.
- Memory/ Storage Technologies
Circuit, architecture, and applications with emerging memory and storage technologies, such as 3D stacking memory, emerging non-volatile memories, and in-memory/in-storage computing technologies.
- Interconnect Technologies
Circuit, architecture, and applications with innovative intra-chip and inter-chip interconnect architecture, including network-on-chip architecture, optical interconnects, and wireless interconnects.
IEEE Fellow, Ph.D. from Princeton University. His research interests include integrated circuit design, electronic design automation, computer architecture, and embedded system design. He has published nearly 300 journal/conference papers.
He is responsible for setting up the chip development engineering team to explore breakthroughs in cutting-edge chip technology and to provide support for a wide range of application scenarios, both within the group and externally. Current development focuses include developing artificial intelligence chips that are applicable to hardware acceleration for cloud-to-end large-scale reasoning and training computation. He once built and led Huawei's technical teams in the US and Shanghai to develop new GPUs and was responsible for the overall architecture design. As a core member of Samsung’s GPU team, he participated in project planning and team forming and was responsible for the design of the top-level architecture, computing core architecture, and instruction set. In the field of heterogeneous computing, graphs and images, and chip technology, he owns over 20 US patents.
He holds a Master's Degree in Electrical Engineering from Texas Tech University; been with S3 Graphics, TSMC, Broadcom, and Qualcomm in Silicon Valley. His major work in computer graphics chip design and specializes in algorithms implementation, data-path design and micro-architecture on whole chip data flow to layout chip floorplan to achieve best PPA. Before join Alibaba, he had re-design whole data-path in Qualcomm graphic core to save over 30% of IP area and 40% of power consumption through multiple generation of Adreno Graphics Core to maintain its competitive edge.
After acquired a Master of Science Degree in Electrical Engineering from the University of Florida, he has witnessed the evolution of the chip industry and specializes in the graphic field. During his experience for more than 20 years, he was focusing on the high-performance and massive parallelism field. Push the tool and design limitation. Before joined Alibaba, he worked in S3 Graphics and AMD, where involved in machine-intelligence product development. Currently, he is responsible for execution technological development of the ASIC team from the scratch in the US.
He graduated from the Institute of VLSI Design, Zhejiang University. He is responsible for the formation of the AliNPU ASIC team in Shanghai. Prior to Alibaba, he worked in S3 Graphics for graphics chip design and then worked at AMD, where he was Director and responsible for the GPU IP design department of the Shanghai R&D Center. There he was involved in the development of the current mainstream graphics chips and dedicated to optimizing chip PPA (performance, power, area). He has rich experience in all aspects of the front and back end of ASIC.
She holds a Master's Degree from Peking University. She is responsible for the Chip Technology Department’s software team, specializing in architecture, compiler, and system performance optimization. She once worked in the graphics chip architecture department of S3 Graphics, responsible for the programmable pipeline and back-end compiler optimization of graphics chips. She then worked in the MLT (Machine Learning and Translation) department of Intel Corp., engaged in binary translation, virtual machines, and spark performance optimization.
Ph.D. from The Pennsylvania State University. His research interests mainly fall into computer architecture, memory subsystem architecture, 3D IC. He has published papers in the top-level conference venues like ISCA and HPCA. He has also received the best paper awards for several times. He used to work for Apple Inc. as a platform architect, where he drafted the iPhone's SoC performance specification and conducted memory performance modeling and evaluation. Prior to Apple, he was a senior architect in Nvidia. He participated in the memory controller's performance modeling and evaluation for both dGPU and Tegra.
ECE Ph.D. from Duke University. He has been working at several design houses such as Nvidia, Altera(Intel), Hisilicon. He has many years of experiences on design, test, reliability, silicon implementation etc. His research interests include high performance and highly reliable IC system design and implementation.
Ph.D. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, in association with the NXP Research. Research Associate with Sakurai Lab, the University of Tokyo; Research Scientist with the Accelerator Team, IBM Research Zurich; Principal Scientist with NXP Research. He has authored or co-authored over 30 scientific publications and hold over 10 US patents. Currently the Associate Editor of the IEEE Transactions on Circuits and Systems (TCAS-I).
Ph.D. from University of Minnesota, at Twin Cities. His research and working experience include high speed VLSI DSP algorithms/architectures with balanced power and area, hardware-friendly algorithm development of complex mathematical models such as those in storage and wireless systems. He worked 7 years in Qualcomm as wireless systems/algorithms engineer. Prior to Qualcomm, he worked in Intel and Marvell as well. He has authored 20 scientific papers and holds 6 US patents.